View MT45W2ML16PFA_1557636.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80be1f7f asynccellularram.fm - rev. a 7/03 en 1 ?2003 micron technology, inc. all rights reserved. 4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary ? asynchronous cellularram tm mt45w4mw16pfa mt45w2mw16pfa mt45w4mv16pfa mt45w2mv16pfa mt45w4ml16pfa MT45W2ML16PFA for the latest data sheet, please refer to micron?s web site: www.micron.com/datasheets features ? asynchronous and page mode interface random access time: 70ns, 85ns page mode read access sixteen-word page size interpage read access: 70ns, 85ns intrapage read access: 20ns, 25ns v cc , v cc q voltages 1.70v?1.95v v cc 1.70v?2.25v v cc q (option w) 2.30v?2.70v v cc q (option v) 2.70v?3.30v v cc q (option l) low power consumption asynchronous read < 25ma intrapage read < 15ma standby: 90a (32mb), 100a (64mb) deep power-down < 10a low-power features temperature compensated refresh (tcr) partial array refresh (par) deep power-down (dpd) mode figure 1: 48-ball fbga n ote: see table 1 on page 3 for ball descriptions. see figure 18 on page 22 for the 48-ball mechanical drawing. note: a part marking guide for the fbga devices can be found on micron?s web site: www.micron.com/numberguide . part number example: MT45W2ML16PFA-70wt options marking v cc core voltage supply 1.8v ? mt45wxmx16pfa w v cc q i/o voltage 3.0v ? mt45wxml16pfa l 2.5v ? mt45wxmv16pfa v 1.8v ? mt45wxmw16pfa w access time 60ns (contact factory) 70ns -70 85ns -85 configuration 4 meg x 16 mt45w4mx16pfa 2 meg x 16 mt45w2mx16pfa package 48-ball fbga fa operating temperature range wireless (-25c to +85c) wt industrial (-40c to +85c) it (contact factory) a b c d e f g h 1 2 3 4 5 6 top view (bump down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 oe# ub# dq10 dq11 dq12 dq13 a19 a8 a0 a3 a5 a17 a21 a14 a12 a9 a2 ce# dq1 dq3 dq4 dq5 we# a11 zz# dq0 dq2 v cc v ss dq6 dq7 a20 a1 a4 a6 a7 a16 a15 a13 a10
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 2 ?2003 micron technology, inc. all rights reserved. general description micron ? cellularram ? products are high-speed, cmos dynamic random access memories that have been developed for low-powe r portable applications. the mt45w4mx16pfa is a 64mb device organized as 4 meg x 16 bits, and the mt45w2mx16pfa is a 32mb device organized as 2 meg x 16 bits. these devices include the industry-standard, asynchronous memory interface found on other low-power sram or pseudo sram offerings. operating voltages have been reduced in an effort to minimize power consumption. the core voltage has been reduced to a 1.80v operating level. to maintain compatibility with different memory bus interfaces, cellularram devices are avai lable with i/o voltages of 3.00v, 2.50v or 1.80v. a user-accessible configuration register (cr) has been included to define device operation. the cr defines how the cellularram device performs on-chip refresh and whether page mode read accesses are per- mitted. this register is au tomatically loaded with a default setting during power-up and can be updated at any time during normal operation. to operate seamlessly on an asynchronous memory bus, cellularram products have incorporated a trans- parent self refresh mechanism. the hidden refresh requires no additional support from the system mem- ory controller and has no significant impact on device read/write performance. special attention has been focused on current con- sumption during self refresh. cellularram products include three system-accessible mechanisms used to minimize refresh current. temperature compensated refresh (tcr) is used to adjust the refresh rate accord- ing to the case temperature. the refresh rate can be decreased at lower temperatures to minimize current consumption during standby. setting the sleep enable pin zz# to low enables one of two low-power modes: partial array refresh (par); or deep power-down (dpd). par limits refresh to only that part of the dram array that contains essential data. dpd halts refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the cr. figure 2: functional block diagram 4 meg x 16 and 2 meg x 16 n ote: functional block diagrams il lustrate simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. a[20:0] (for 32mb) a[21:0] (for 64mb) input/ output mux and buffers control logic 2,048k x 16 (4,096k x 16) dram memory array dq[7:0 ] dq[15: 8] address decode logic lb# ub# ce# w e# oe# zz# configuration register (cr)
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 3 ?2003 micron technology, inc. all rights reserved. n ote: 1. when lb# and ub# are in select mode (low), dq[15:0] are affected. when lb# only is in select mode, only dq[7:0] are affected. when ub# only is in th e select mode, dq[15:8] are affected. 2. when the device is in standby mode, control inputs (w e#, oe#), address inputs, and data inputs/outputs are inter- nally isolated from an y external influence. 3. when we# is invoked, the oe# in put is internally di sabled and has no effect on the i/os. 4. the device will cons ume active power in this mode whenever addresses are changed. 5. v in = v cc or 0v; all device balls must be static (unswitc hed) in order to achiev e minimum standby current. 6. dpd is enabled when configur ation register bit cr[4] is ?0?; otherwise, par is enabled. table 1: fbga ball descriptions fbga ball assignment symbol type description a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4, e4, d3, h1, g2, h6, e3 a[21:0] input address inputs: inputs for the address acce ssed during read or write operations. the address lines are also used to defi ne the value to be loaded into the configuration register. on the 32mb devi ce, a21 (ball e3) is not internally connected. a6 zz# input sleep enable: when zz# is low, the conf iguration register can be loaded or the device can enter one of two lo w-power modes (dpd or par). b5 ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby power mode. a2 oe# input output enable: enables the output buffers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: enables write operations when low. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] b6, c5, c6, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 dq[15:0] input/ output data inputs/outputs. d6 v cc supply device power supply: (1.7v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.8v, 2.5v, 3.0v) power supply for input/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. table 2: bus operations mode power ce# we# oe# lb#/ub# zz# dq[15:0] 1 notes standby standby h x x x h high-z 2, 5 read active > standby l h l lh data-out 1, 4 write active > standby l l x lh data-in 1, 3, 4 active standby l h h l h high-z 4, 5 par partial array refresh h x x x l high-z 6 dpd deep power-down h x x x l high-z 6 load configuration register active l l x x l high-z
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 4 ?2003 micron technology, inc. all rights reserved. n ote: 1. contact factory for availability. table 3: abbreviated component marks? cellularram fbga-packaged components part number engineering sample qualified sample mt45w4mw16pfa-85 wt px300 pw300 mt45w4mw16pfa-70 wt px306 pw306 mt45w4ml16pfa-85 wt px303 pw303 mt45w4ml16pfa-70 wt px304 pw304 mt45w2mw16pfa-85 wt px200 pw200 mt45w2mw16pfa-70 wt px206 pw206 MT45W2ML16PFA-85 wt px203 pw203 MT45W2ML16PFA-70 wt px204 pw204 mt45w4mw16pfa-85 it px348 1 pw348 1 mt45w4mw16pfa-70 it px349 1 pw349 1 mt45w4ml16pfa-85 it px350 1 pw350 1 mt45w4ml16pfa-70 it px351 1 pw351 1 mt45w2mw16pfa-85 it px207 1 pw207 1 mt45w2mw16pfa-70 it px208 1 pw208 1 MT45W2ML16PFA-85 it px209 1 pw209 1 MT45W2ML16PFA-70 it px210 1 pw210 1
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 5 ?2003 micron technology, inc. all rights reserved. functional description in general, the mt45w4mx16pfa device and the mt45w2mx16pfa device are high-density alternatives to sram and pseudo sram products, popular in low- power, portable applications. the mt45w4mx16pfa contains 67,108,864 bits organized as 4,194,304 addresses by 16 bits. the mt45w2mx16pfa contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. these devices include the industry-standard, asyn- chronous memory interface found on other low-power sram or pseudo sram offerings. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products incl ude an on-chip voltage sensor that is used to laun ch the power-up initializa- tion process. initialization will load the cr with its default settings. v cc and v cc q must be applied simul- taneously, and when they reach a stable level above 1.70v, the device will require 150s to complete its self- initialization process (see figure 3 below). during the initialization period, ce# should remain high. when initialization is complete, the device is ready for nor- mal operation. at power-up, the cr is set to 0070h. figure 3: power-up initialization timing bus operating modes the mt45w4mx16pfa and the mt45w2mx16pfa cellularram products incorporate the industry-stan- dard, asynchronous interface found on other low- power sram or pseudo sram offerings. this bus interface supports asynchronous read and write operations as well as the bandwidth-enhancing page mode read operation. the specific interface that is supported is defined by the value loaded into the cr. asynchronous mode cellularram products power up in the asynchro- nous operating mode. this mode uses the industry- standard sram control interface (ce#, oe#, we#, lb#/ ub#). read operations (figure 4) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 5) occu r when ce#, we#, and lb#/ ub# are driven low. during write operations, the level of oe# is a ?don't care?; we# will override oe#. the data to be written will be latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). figure 4: read operation figure 5: write operation vcc v ccq device initialization vcc = 1.7v device ready for normal operation t pu > 150 s address valid data ce# don?t car e data valid oe# we# lb#/ub# t rc = read cycle time a ddress address valid data ce# don?t car e data valid oe# we# lb#/ub# t wc = write cycle time a ddress
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 6 ?2003 micron technology, inc. all rights reserved. page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. addresses a[4] and higher must remain fixed during the entire page mode access. figure 6 shows the timing diagram for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write op erations do not include comparable page mode functionality. figure 6: page read operation lb#/ub# operation the lower byte (lb#) enable and upper byte (ub#) enable signals allow for byte-wide data transfers. dur- ing read operations, enabled bytes are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operation. dur- ing write operations, any disabled bytes will not be transferred to the memory array and the internal value will remain unchanged. during a write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, the device remains in an active mode as long as ce# remains low. low power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation on the full array. standby operation occurs when ce# and zz# are high and there are no transactions in progress. the device will enter standby operation during read and write operations where the address and control inputs remain static for an extended period of time. this ?active? standby mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate depending on the device operat- ing temperature. dram technology requires more fre- quent refresh operations to maintain data integrity as temperatures increase. more frequent refresh is required due to the increa sed leakage of the dram's capacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will facili- tate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds: +15c, +45c, +70c, and +85c. the setting selected must be for a temperature higher than the case temperature of the cellularram device. if the case temperature is +50c, the system can minimize self refresh current consumption by selecting the +70c setting. the +15c and +45c set- tings would result in inadequate refreshing and cause data corruption. partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the system to reduce refresh current by only refreshing that part of the memory array that is abso- lutely necessary. the refresh options are full array, three-quarters array, one-half array, one-quarter array, or none of the array. data stored in addresses not receiving refresh will become corrupted. the mapping of these partitions can start at either the beginning or the end of the address map (tables 5 and 6). read and write operations are ignored during par operation. the device can only enter par mode if the sleep bit in the configuration register has been set high (cr[4] = 1). par is initiated by bring the zz# pin to the low state for longer than 10s. returning zz# to high will add0 data ce# don?t car e oe# we# lb#, ub# a ddress add[0] add[1] add[2] add[3] d[1] d[2] d[3] t aa t apa t apa t apa d[0]
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 7 ?2003 micron technology, inc. all rights reserved. cause an exit from par and the entire array will be immediately available for read and write opera- tions. deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used when the system does not require the storage provided by the cellularram device. any stored data will become cor- rupted when dpd is entered. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initia lization procedure before normal operations can resume. read and write operations are ignored during dpd operation. the device can only enter dpd if the sleep bit in the cr has been set low (cr[4] = 0). dpd is initiated by bringing the zz# pin to the low state for longer than 10s. returning zz# to high will cause the device to exit dpd and begin a 150s initialization pro- cess. during this 150s period, the current consump- tion will be higher than the specified standby levels but considerably lower than the active current specifica- tion. driving the zz# pin low will place the device in the par mode if the sleep bit in the cr has been set high (cr[4] = 1).
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 8 ?2003 micron technology, inc. all rights reserved. configuration register operation the configuration register (cr) defines how the cel- lularram device performs its transparent self refresh. this register is automatically loaded with default set- tings during power-up and can be updated anytime while the device is operating in a standby state. the cr is loaded using a write operation immedi- ately after zz# makes a high-to-low transition (figure 7). the values placed on addresses a[21:0] are latched into the cr on the rising edge of ce# or we#, whichever occurs first. altering the refresh parameters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the configuration register. table 4 on page 9 describes the control bits used in the cr. at power up, the cr is set to 0070h. figure 7: load configuration register operation partial array refresh (cr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the sys- tem to reduce current by only refreshing that part of the memory array required by the host system. the refresh options are full array, three-quarters array, one- half array, one-quarter array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables 5 and 6 on page 9). sleep mode (cr[4]) default = par enabled, dpd disabled the sleep mode bit determines which low-power mode is to be entered when zz# is driven low. if cr[4] = 1, par operation is enabled. if cr[4] = 0, dpd opera- tion is enabled. dpd operation disables all refresh-related activity. this mode will be used when the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re- enabled, the cellularram device will require 150s to perform an initialization procedure before normal operation can resume. temperature compensated refresh (cr[6:5]) default = +85c operation the tcr bits allow for adequate refresh at four differ- ent temperature thresholds: +15c, +45c, +70c, and +85c. the setting selected must be for a temperature higher than the case temperature of the cellularram device. if the case temperatur e is +50c, the system can minimize self refresh current consumption by selecting the +70c setting. the +15c and +45c settings would result in inadequate refreshing and cause data corrup- tion. page mode read operation (cr[7]) default = disabled the page mode operation bit determines whether page mode read operations are enabled. in the power-up default state, page mode is disabled. address valid ce# zz# we# t < 500ns a ddress
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 9 ?2003 micron technology, inc. all rights reserved. table 4: configuration register bit mapping par a4 a3 a2 a1 a0 configuration register address bus 4 1 2 3 0 reserved 6 5 a5 0 1 sleep mode dpd enabled par enabled (default) cr[4] tcr cr[6] cr[5] 11 1 1 00 0 0 maximum case temp. +85?c (default) +70?c +45?c +15?c a6 21? 8 reserved a[21:8] cr[1] 0 0 1 1 cr[0] 0 1 0 1 par refresh coverage full array (default) bottom 3/4 array bottom 1/2 array bottom 1/4 array cr[2] 0 0 0 0 00 1 01 1 1 0 1 11 1 none of array top 3/4 array top 1/2 array top 1/4 array sleep must be set to "0" all must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enabled cr[7] table 5: 32mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 000000h?1ff fffh 2 meg x 16 32mb 0 0 1 three-quarters of die 000000h?17ffffh 1.5 meg x 16 24mb 0 1 0 one-half of die 00000 0h?0fffffh 1 meg x 16 16mb 0 1 1 one-quarter of die 000000h?07ffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 08 0000h?1fffffh 1.5 meg x 16 24mb 1 1 0 one-half of die 10000 0h?1fffffh 1 meg x 16 16mb 1 1 1 one-quarter of die 18 0000h?1fffffh 512k x 16 8mb table 6: 64mb address patterns for par (cr[4] = 1) cr[2] cr[1] cr[0] active section address space size density 0 0 0 full die 000000h-3fffffh 4 meg x 16 64mb 0 0 1 three-quarters of die 000000h-2fffffh 3 meg x 16 48mb 0 1 0 one-half of die 000000h-1fffffh 2 meg x 16 32mb 0 1 1 one-quarter of die 000000h-0fffffh 1 meg x 16 16mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 three-quarters of die 100000h-3fffffh 3 meg x 16 48mb 1 1 0 one-half of die 200000h-3fffffh 2 meg x 16 32mb 1 1 1 one-quarter of die 300000h-3fffffh 1 meg x 16 16mb
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 10 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings* voltage to any ball except v cc , v cc q relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50v to (4.0v or vccq + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . -0.20v to 2.45v voltage on v cc q supply relative to v ss . -0.20v to 4.0v storage temperature . . . . . . . . . . . . . . . . -55 c to 150 c operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . -25 c to 85 c industrial . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to 85 c soldering temperature and time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . .260 c *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. n ote: 1. this parameter is specified with the outputs disabl ed to avoid external loading ef fects. the user must add current required to drive output capacitanc e expected in the actual system. 2. this device assumes a standby mode if the chip is disabled (ce# high). it will also automatically go into a standby mode whenever all input signals are quie scent (not toggling), regard less of the state of ce#, lb#, and ub#. in order to achieve low standby current, all inputs must be either v cc q or v ss . 3. i sb (max) values measured with par se t to full array and tcr set to +85c. table 7: electrical characteri stics and operating conditions wireless temperature (-25oc t c +85 oc) industrial temperature (-40oc < t c < +85oc) description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage l: 3.00v v cc q2.703.30v v: 2.50v v cc q2.302.70v w:1.80v v cc q1.702.25v input high voltage v ih 1.4 v cc q + 0.2 v input low voltage v il -0.2 +0.4 v output high voltage i oh = -0.2ma v oh 0.80 v cc qv output low voltage i ol = 0.2ma v ol 0.20 v cc qv input leakage current v in = 0 to v cc qi li 1 a output leakage current oe# = v ih or chip disabled i lo 1 a2 read operating current v in = v cc q or 0v chip enabled, i out = 0 i cc 1 -70 25 ma 1, 2 -85 20 ma 1, 2 write operating current v in = v cc q or 0v chip enabled i cc 2 -70 25 ma 1, 2 -85 20 ma 1, 2 max standby current v in = v cc q or 0v chip disabled i sb 32mb 90 a2, 3 64mb 100 a2, 3
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 11 ?2003 micron technology, inc. all rights reserved. n ote: 1. i tcr (max) values measured with full array refresh. 2. this device assumes a standby mode if the chip is disabled (ce# high). it will also automatically go into a standby mode whenever all input signals are quie scent (not toggling), regard less of the state of ce#, lb#, and ub#. in order to achieve low standby current, all inputs must be either v cc q or v ss . n ote: i par (max) values measured with tcr set to 85c. table 8: temperature compensated re fresh specifications and conditions description conditions symbol density max case temperatures typ max units temperature compensated refresh standby current v in = v cc q or 0v, chip disabled i tcr 64mb +85c 100 a +70c tbd a +45c tbd a +15c 50 a 32mb +85c 90 a +70c tbd a +45c tbd a +15c 50 a table 9: partial array refresh specifications and conditions description conditions symbol density array partition typ max units partial array refresh current v in = v cc q or 0v zz# = low cr[4] = 1 i par 64mb full 100 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 050a 32mb full 90 a 3/4 tbd a 1/2 tbd a 1/4 tbd a 050a table 10: deep power-down sp ecifications and conditions description conditions symbol typ max units deep power-down v in = v cc q or 0v; +25c zz# = low cr[4] = 0 i zz 10 a
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 12 ?2003 micron technology, inc. all rights reserved. n ote: 1. these parameters are verified in device characterization and are not 100% tested. figure 8: ac input/ou tput reference waveform n ote: ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input timing begins at v cc q/2, and output timing ends at v cc q/2. input rise an d fall times (10% to 90%) < 1.6ns. figure 9: output load circuit table 11: capacitance specifications and conditions description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in ?6pf1 input/output capacitance (dq) c io ?6pf1 v ccq vccq/2 outpu t v ss input vccq/2 test points dut vccq r1 r2 30pf test poin t table 12: output load circuit v cc q r1/r2 1.8v 2.7k ? 2.5v 3.7k ? 3.0v 4.5k ?
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 13 ?2003 micron technology, inc. all rights reserved. n ote: 1. high-z to low-z timings are tested with the circuit shown in figure 9 on page 12. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested wi th the circuit shown in figure 9 on page 12. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. table 13: read cycle timing requirements parameter symbol -70 -85 units notes min max min max address access time t aa 70 85 ns page access time t apa 20 25 ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to high-z output t bhz 0808ns2 lb#/ub# enable to low-z output t blz 10 10 ns 1 chip select access time t co 70 85 ns chip disable to high-z output t hz 0808ns2 chip enable to low-z output t lz 10 10 ns 1 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to high-z output t ohz 0808ns2 output enable to low-z output t olz 55ns1 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns table 14: write cycle timing requirements parameter symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns byte select to end of write t bw 70 85 ns ce# high time during write t ceh 55ns maximum ce# pulse width t cem 10 10 s chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 25 ns chip enable to low-z output t lz 10 10 ns 1 end write to low-z output t ow 55ns write cycle time t wc 70 85 ns write to high-z output t whz 0808ns2 write pulse width t wp 46 50 ns write recovery time t wr 00ns
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 14 ?2003 micron technology, inc. all rights reserved. table 15: load configuration re gister timing requirements description symbol -70 -85 units notes min max min max address setup time t as 00ns address valid to end of write t aw 70 85 ns chip deselect to zz# low t cdzz 55ns chip enable to end of write t cw 70 85 ns write cycle time t wc 70 85 ns write pulse width t wp 40 40 ns write recovery time t wr 00ns zz# low to we# low t zzwe 10 500 10 500 ns table 16: deep power-down timing requirements description symbol -70 -85 units notes min max min max chip deselect to zz# low t cdzz 55ns deep power-down recovery t r 150 150 s minimum zz# pulse width t zzmin 10 10 s table 17: power-up initializ ation timing requirements parameter symbol -70 -85 units notes min max min max power-up initialization period t pu 150 150 s
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 15 ?2003 micron technology, inc. all rights reserved. figure 10: power-up initialization period figure 11: load con figuration register device ready fo r normal operatio n vcc, vccq = 1.7v t pu vcc (min) table 18: initializatio n timing parameters symbol -70 -85 units min max min max t pu 150 150 s a ddress zz# t wc t aw t wr t as ce# lb#/ub# t zzwe don?t car e we# t wp t cdzz opcode t cw oe# table 19: load configuration re gister timing requirements symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t wc 70 85 ns t aw 70 85 ns t wp 40 40 ns t cdzz 55ns t wr 00ns t cw 70 85 ns t zzwe 1050010500ns
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 16 ?2003 micron technology, inc. all rights reserved. figure 12: deep powe r-down ? entry/exit z z# c e# t zz (min) don?t car e t cdzz t r device ready for normal operatio n table 20: deep power-down timing parameters symbol -70 -85 units min max min max t cdzz 55ns t r 150 150 s t zz (min) 10 10 s
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 17 ?2003 micron technology, inc. all rights reserved. figure 13: single re ad operation (we# = v ih ) address oe# t rc t aa d ata-out ce# lb#/ub# t olz t lz don?t care undefined high-z data valid t ohz t ba t bhz t hz t blz t co t oe high-z address valid table 21: read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 0808ns t ohz 0808ns t blz 10 10 ns t olz 55ns t co 70 85 ns t rc 70 85 ns t hz 0808ns
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 18 ?2003 micron technology, inc. all rights reserved. figure 14: page mode read operation (we# = v ih ) address a[21:4] oe# t aa d ata-out ce# lb#/ub# t olz t lz don?t care undefined high-z data valid t ohz t ba t bhz t hz t blz t co address a[3:0] data valid data valid data valid t rc t oh high-z t pc address valid t apa t oe table 22: page mode read timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t aa 70 85 ns t lz 10 10 ns t apa 20 25 ns t oe 20 20 ns t ba 70 85 ns t oh 55ns t bhz 0 8 0 8 ns t ohz 0 8 0 8 ns t blz 10 10 ns t olz 55ns t co 70 85 ns t pc 20 25 ns t hz 0 8 0 8 ns t rc 70 85 ns
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 19 ?2003 micron technology, inc. all rights reserved. figure 15: write cycle (we# control) address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t ow t dh t dw t as t wp don?t car e high-z d ata-out data valid t cw t cem oe# address valid table 23: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t ow 55ns t bw 70 85 ns t wc 70 85 ns t cem 10 10 s t whz 0808ns t cw 70 85 ns t wp 46 50 ns t dh 00ns t wr 00ns
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 20 ?2003 micron technology, inc. all rights reserved. figure 16: write cycle (ce# control) address we# t wc t aw t cw t cem t wr t ceh data-in ce# lb#/ub# t bw t whz t lz t as t dh t dw t wp don?t car e high-z d ata-out data valid oe# table 24: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t ceh 55ns t whz 080 ns t cem 10 10 s t wp 46 50 ns t cw 70 85 ns t wr 00ns t dh 00ns
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 21 ?2003 micron technology, inc. all rights reserved. figure 17: write cycle (lb#/ub# control) address we# t wc t aw t wr data-in ce# lb#/ub# t bw t whz t dh t as t dw t lz don?t car e d ata-out data valid t cem oe# high-z table 25: write timing parameters symbol -70 -85 units symbol -70 -85 units min max min max min max min max t as 00ns t dw 23 25 ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cem 10 10 s t whz 0808ns t dh 00ns t wr 00ns
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, and the micron and m logos are trademarks and/or service marks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all other trademarks are the property of their respective owners. 4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 22 ?2003 micron technology, inc. all rights reserved. figure 18: 48-ball fbga n ote: 1. all dimensions in millimeters, max/min or typical where noted. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. data sheet designation: preliminary this data sheet contains initial characterization limits, subject to change up on full characterization of production devices. 0.700 0.075 0.10 c c solder ball material: eutectic 63% sn, 37% pb or 62% sn, 36% pb, 2% ag solder ball pad: ? .27mm ball a1 id encapsulation material: epoxy novola c substrate: plastic laminate 0.75 typ 8.00 0.10 ball a1 id 0.75 typ 0.35 typ 48x ? 1.00 max s eating plane ball a6 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.33 ball a1 5.25 2.625 0.05 1.875 0.050 3.00 0.05 6.00 0.10 4.00 3.75
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 23 ?2003 micron technology, inc. all rights reserved. appendix a how extended timings impact cellularram tm operation introduction cellularram ? products use a dram technology that periodically requires refresh to ensure against data corruption. cellularra m devices include on-chip circuitry that performs the required refresh in a man- ner that is completely transparent in systems with nor- mal bus timings. the refresh circuitry does impose constraints on timings in sy stems that take longer than 10s to complete write operations. this appendix describes cellularram timing requirements in sys- tems that perform extended operations. operation when page mode is disabled cellularram products requ ire that all write opera- tions must be completed wi thin 10s. after completing an operation, the device must either enter standby (by transitioning ce# high), or else perform a second operation using a new address. figures 19 and 20 dem- onstrate these constraints as they apply during an asynchronous (page-mode-dis abled) operation. either the ce# active period ( t cem in figure 19) or the address valid period ( t tm in figure20) must be less than 10s during any operation to accommodate orderly scheduling of refresh. figure 19: extended timing for t cem n ote: timing constraints when pa ge mode is disabled. figure 20: extended timing for t tm n ote: timing constraints when pa ge mode is disabled. operation when page mode is enabled when a cellularram device is configured for page mode operation, the address inputs are used to accel- erate read accesses and cannot be used by the on-chip circuitry to schedule refresh. ce# must return high upon completion of all write operations when page mode is enabled (figure 21). the total time taken for a write operation should not exceed 10s to accom- modate orderly scheduling of refresh. figure 21: extended timing for t cem n ote: timing constraints when page mode is enabled. impact on extended write operations modified timings are only required during extended write operations (see figure 22 below). an extended write operation requires th at both the write pulse width ( t wp) and the data valid period ( t dw) will need to be lengthened to at least the minimum write cycle time ( t wc [min]). these increased timings ensure that time is available for both a refresh operation and suc- cessful completion of the write operation. figure 22: extended write operation ce# a ddress t cem 10s < ce# a ddress < t tm 10 s c e# t cem 10s < data valid data-in a ddress ce# lb#/ub# we# t cem or t tm > 10s t wp t wc (min) > t dw t wc (min) >
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 24 ?2003 micron technology, inc. all rights reserved. summary cellularram products are desi gned to ensure that any possible bus timings do not cause corruption of array data due to lack of refresh. the on-chip refresh circuitry will only affect the requir ed timings for write opera- tions (reads are unaffected) performed in a system with a slow memory interface. the impact for write oper- ations is that some of the timing parameters ( t wp, t dw) are lengthened. the modified timings are likely to have little or no impact when interfacing a cellular- ram device with a low-speed memory bus.
4 meg x 16, 2 meg x 16 async/page cellularram memory preliminary 09005aef80be1f7f micron technology, inc., reserves the right to change products or specifications without notice. asynccellularram.fm - rev. a 7/03 en 25 ?2003 micron technology, inc. all rights reserved. table 26: revision history change date changed by description 7 07/10/03 ddb input/output leakage to 1a. 6 6/23/03 ddb incorporated industrial temper ature data where applicable. 5 6/20/03 ddb added condition zz# low to par and dpd tables. 4 6/19/03 ddb changed standby power to 90a and 1 00a respectively; changed specified values to ?tbd.? moved lb#/ub# rising edge back in write operation diagram. 3 06/09/03 ddb absolute maximum signal input value changed. 2 06/06/03 ddb edits suggested 6/6: electrical characteristics and operating conditions (table 7 on page 10), changed input high voltage max to vccq + 0.2, output high voltage and output low voltage presentation changed for consistency. 1 06/05/03 ddb initial release.

▲Up To Search▲

Price & Availability of MT45W2ML16PFA

	To Download MT45W2ML16PFA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .